1. Field of the Invention.
The present invention relates to analog to digital converters, and more particularly, to dual slope analog to digital converters.
2. Discussion of the Background of the Invention.
Analog to digital converters convert an unknown analog input signal, such as an unknown voltage signal, to a digital representation of that unknown signal. Dual slope A/D converters typically include an integrator which integrates the unknown voltage over a fixed period of time which is usually referred to as the integrate cycle. During a subsequent deintegrate or timing cycle, the integrated signal is deintegrated by a known reference voltage for a variable period of time which is terminated when the deintegrated signal as sensed by a comparator reaches a predetermined level which is usually zero volts. The duration of the deintegrate cycle is proportional to the analog input voltage since the ratio of the input voltage to the reference voltage is equal to the ratio of the deintegrate cycle to the integrate cycle. The duration of the deintegrate cycle can be measured by counting clock pulses, which provides a digital representation of the analog input voltage.
One limitation on the rate at which many dual slope A/D converters can convert an analog input voltage to a digital representation is the finite response time of the comparator which detects the zero crossing of the deintegrated signal. The comparator response time is in turn related to a factor often referred to as the system "overdrive" which is the maximum voltage that the integrator can charge up to divided by the system resolution. Generally, the larger the system overdrive, the faster the comparator can correctly detect a zero crossing of the deintegrated signal. However, the maximum integrator voltage is typically limited by the power supply voltage of the system. Accordingly, in order to increase the response time of the comparator, it is often been necessary for many previous dual slope A/D converters to increase the supply voltage to the integrator of the converter system. Increasing the power supply voltage can increase power consumption as well as further complicate the design of the overall system.
Other techniques for improving the comparator response time (or decreasing the sensitivity of the system to this response time) have included adding external components or precisely matching certain elements. Such techniques can similarly increase design complexity and increase the costs of manufacture as well.